Simulation results demonstrate high signal-to-error ratio and fault tolerance in these structures. Furthermore, hardware synthesis results show that these filter structures require lower hardware area and power compared to two's complement realizations. Second, We present stochastic logic implementations of complex arithmetic functions based on truncated versions of their Maclaurin series expansions.
It is shown that a polynomial can be implemented using multiple levels of NAND gates based on Horner's rule, if the coefficients are alternately positive and negative and their magnitudes are monotonically decreasing. Truncated Maclaurin series expansions of arithmetic functions are used to generate polynomials which satisfy these constraints.
The input and output in these functions are represented by unipolar representation. For a polynomial that does not satisfy these constraints, it still can be implemented based on Horner's rule if each factor of the polynomial satisfies these constraints. Polynomials are transformed to equivalent forms that naturally exploit format conversions.
The proposed stochastic logic circuits outperform the well-known Bernstein polynomial based and finite-state-machine FSM based implementations. Furthermore, the hardware complexity and the critical path of the proposed implementations are less than the Bernstein polynomial based and FSM based implementations for most cases.
Third, we address subtraction and polynomial computations using unipolar stochastic logic. It is shown that stochastic computation of polynomials can be implemented by using a stochastic subtractor and factorization. Two approaches are proposed to compute subtraction in stochastic unipolar representation. In the first approach, the subtraction operation is approximated by cascading multi-levels of OR and AND gates. The accuracy of the approximation is improved with the increase in the number of stages.
In the second approach, the stochastic subtraction is implemented using a multiplexer and a stochastic divider. We propose stochastic computation of polynomials using factorization. Stochastic implementations of first-order and second-order factors are presented for different locations of polynomial roots. From experimental results, it is shown that the proposed stochastic logic circuits require less hardware complexity than the previous stochastic polynomial implementation using Bernstein polynomials.
Finally, this thesis presents novel architectures for machine learning based classifiers using stochastic logic. Three types of classifiers are considered. These architectures are validated using seizure prediction from electroencephalogram EEG as an application example.
To improve the accuracy of proposed stochastic classifiers, an approach of data-oriented linear transform for input data is proposed for EEG signal classification using linear SVM classifiers. Simulation results in terms of the classification accuracy are presented for the proposed stochastic computing and the traditional binary implementations based datasets from two patients.
It is shown that accuracies of the proposed stochastic linear SVM are improved by 3. Compared to conventional binary implementation, the accuracy of the proposed stochastic ANN is improved by 5. For patient-2, the accuracy of the proposed stochastic ANN is improved by 7. Additionally, compared to the traditional binary linear SVM and ANN, the hardware complexity, power consumption and critical path of the proposed stochastic implementations are reduced significantly.
Keywords Digital signal processing. Appears in collections Dissertations . PhD thesis. Here you can download a pdf-file of my thesis: Algorithms for the Constrained Design of Digital Filters with Arbitrary Magnitude and Phase Responses All Matlab files used in the thesis can be downloaded here.
Abstract: This thesis presents several new algorithms for designing digital filters subject to specifications in the frequency domain. Unlike many standard filter design algorithms, all methods proposed here solve the problem of simultaneously approximating specified magnitude and phase responses. Filters of this type can be used to optimally equalize magnitude and phase distortions. Such problems occur e. Another application of the proposed algorithms is the design of filters with low group delay in the passbands.
In the FIR case, the exactly linear phase property is given up in order to reduce the delay while maintaining a good approximation to phase linearity in the passbands. IIR filters can also be designed to have an approximately linear passband phase response. Their passband group delay is usually considerably smaller than the delay of linear phase FIR filters with equivalent magnitude responses. An important feature of the algorithms presented in this thesis is that they allow for design constraints which often arise in practical filter design problems.